View M93C06-TRMN6T_6841271.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/27 may 2003 m93c86, m93c76, m93c66 m93c56, m93c46, m93c06 16kbit, 8kbit, 4kbit, 2kbit, 1kbit and 256bit (8-bit or 16-bit wide) microwire serial access eeprom features summary n industry standard microwire bus n single supply voltage: C 4.5v to 5.5v for m93cx6 C 2.5v to 5.5v for m93cx6-w C 1.8v to 5.5v for m93cx6-r n dual organization: by word (x16) or byte (x8) n programming instructions that work on: byte, word or entire memory n self-timed programming cycle with auto-erase n ready/busy signal during programming n speed: C 1mhz clock rate, 10ms write time (current product, identified by process identification letter f or m) C 2mhz clock rate, 5ms write time (new product, identified by process identification letter w) n sequential read operation n enhanced esd/latch-up behaviour n more than 1 million erase/write cycles n more than 40 year data retention figure 1. packages m93c06 is not for new design the m93c06 is still in production, but is not recom- mended for new designs. please refer to an1571 on how to replace the m93c06 by the m93c46 in your application. pdip8 (bn) 8 1 so8 (mn) 150 mil width 8 1 tssop8 (dw) 169 mil width tssop8 (ds) 3x3mm body size
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 2/27 summary description these electrically erasable programmable memo- ry (eeprom) devices are accessed through a se- rial data input (d) and serial data output (q) using the microwire bus protocol. figure 2. logic diagram table 1. signal names the memory array organization may be divided into either bytes (x8) or words (x16) which may be selected by a signal applied on organization se- lect (org). the bit, byte and word sizes of the memories are as shown in table 2. table 2. memory size versus organization note: 1. not for new design the m93cx6 is accessed by a set of instructions, as summarized in table 3, and in more detail in table 4 to table 6). table 3. instruction set for the m93cx6 a read data from memory (read) instruction loads the address of the first byte or word to be read in an internal address register. the data at this address is then clocked out serially. the ad- dress register is automatically incremented after the data is output and, if chip select input (s) is held high, the m93cx6 can output a sequential stream of data bytes or words. in this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the m93c86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached). programming is internally self-timed (the external clock signal on serial clock (c) may be stopped or left running after the start of a write cycle) and does not require an erase cycle prior to the write instruction. the write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the m93cx6. after the start of the programming cy- s chip select input d serial data input q serial data output c serial clock org organisation select v cc supply voltage v ss ground ai01928 d v cc m93cx6 v ss c q s org device number of bits number of 8-bit bytes number of 16-bit words m93c86 16384 2048 1024 m93c76 8192 1024 512 m93c66 4096 512 256 m93c56 2048 256 128 m93c46 1024 128 64 m93c06 1 256 32 16 instruction description data read read data from memory byte or word write write data to memory byte or word ewen erase/write enable ewds erase/write disable erase erase byte or word byte or word eral erase all memory wral write all memory with same data
3/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 cle, a busy/ready signal is available on serial data output (q) when chip select input (s) is driv- en high. an internal power-on data protection mechanism in the m93cx6 inhibits the device when the supply is too low. figure 3. dip, so and tssop connections note: 1. see page 21 (onwards) for package dimensions, and how to identify pin-1. 2. du = do nt use. figure 4. 9 0 turned-so connections note: 1. see page 24 for package dimensions, and how to identify pin-1. 2. du = dont use. the du (dont use) pin does not contribute to the normal operation of the device. it is reserved for use by stmicroelectronics during test sequences. the pin may be left unconnected or may be con- nected to v cc or v ss . direct connection of du to v ss is recommended for the lowest stand-by pow- er consumption. memory organization the m93cx6 memory is organized either as bytes (x8) or as words (x16). if organization select (org) is left unconnected (or connected to v cc ) the x16 organization is selected; when organiza- tion select (org) is connected to ground (v ss ) the x8 organization is selected. when the m93cx6 is in stand-by mode, organization select (org) should be set either to v ss or v cc for minimum power consumption. any voltage between v ss and v cc applied to organization select (org) may increase the stand-by current. power-on data protection to prevent data corruption and inadvertent write operations during power-up, a power-on reset (por) circuit resets all internal programming cir- cuitry, and sets the device in the write disable mode. C at power-up and power-down, the device must not be selected (that is, chip select input (s) must be driven low) until the supply voltage reaches the operating value v cc specified in table 8 to table 10. C when v cc reaches its valid level, the device is properly reset (in the write disable mode) and is ready to decode and execute incoming in- structions. for the m93cx6 devices (5v range) the por threshold voltage is around 3v. for the m93cx6- w (3v range) and m93cx6-r (2v range) the por threshold voltage is around 1.5v. v ss q org du c sv cc d ai01929b m93cx6 1 2 3 4 8 7 6 5 1 v ss q org du c s v cc d ai00900b m93cx6 2 3 4 8 7 6 5
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 4/27 instructions the instruction set of the m93cx6 devices con- tains seven instructions, as summarized in table 4 to table 6. each instruction consists of the follow- ing parts, as shown in figure 5: n each instruction is preceded by a rising edge on chip select input (s) with serial clock (c) being held low. n a start bit, which is the first 1 read on serial data input (d) during the rising edge of serial clock (c). n two op-code bits, read on serial data input (d) during the rising edge of serial clock (c). (some instructions also use the first two bits of the address to define the op-code). n the address bits of the byte or word that is to be accessed. for the m93c46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see table 4). for the m93c56 and m93c66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see table 5). for the m93c76 and m93c86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see table 6). the m93cx6 devices are fabricated in cmos technology and are therefore able to run as slow as 0 hz (static input signals) or as fast as the max- imum ratings specified in table 19 to table 22. table 4. instruction set for the m93c46 and m93c06 note: 1. x = don't care bit. 2. address bits a6 and a5 are not decoded by the m93c06. 3. address bits a5 and a4 are not decoded by the m93c06. instruc tion description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address 1,2 data required clock cycles address 1,3 data required clock cycles read read data from memory 1 10 a6-a0 q7-q0 a5-a0 q15-q0 write write data to memory 1 01 a6-a0 d7-d0 18 a5-a0 d15-d0 25 ewen erase/write enable 1 00 11x xxxx 10 11 xxxx 9 ewds erase/write disable 1 00 00x xxxx 10 00 xxxx 9 erase erase byte or word 1 11 a6-a0 10 a5-a0 9 eral erase all memory 1 00 10x xxxx 10 10 xxxx 9 wral write all memory with same data 1 00 01x xxxx d7-d0 18 01 xxxx d15-d0 25
5/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 table 5. instruction set for the m93c56 and m93c66 note: 1. x = don't care bit. 2. address bit a8 is not decoded by the m93c56. 3. address bit a7 is not decoded by the m93c56. table 6. instruction set for the m93c76 and m93c86 note: 1. x = don't care bit. 2. address bit a10 is not decoded by the m93c76. 3. address bit a9 is not decoded by the m93c76. instruc tion description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address 1,2 data required clock cycles address 1,3 data required clock cycles read read data from memory 1 10 a8-a0 q7-q0 a7-a0 q15-q0 write write data to memory 1 01 a8-a0 d7-d0 20 a7-a0 d15-d0 27 ewen erase/write enable 1 00 1 1xxx xxxx 12 11xx xxxx 11 ewds erase/write disable 1 00 0 0xxx xxxx 12 00xx xxxx 11 erase erase byte or word 1 11 a8-a0 12 a7-a0 11 eral erase all memory 1 00 1 0xxx xxxx 12 10xx xxxx 11 wral write all memory with same data 100 0 1xxx xxxx d7-d0 20 01xx xxxx d15-d0 27 instruc tion description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address 1,2 data required clock cycles address 1,3 data required clock cycles read read data from memory 1 10 a10-a0 q7-q0 a9-a0 q15-q0 write write data to memory 1 01 a10-a0 d7-d0 22 a9-a0 d15-d0 29 ewen erase/write enable 1 00 11x xxxx xxxx 14 11 xxxx xxxx 13 ewds erase/write disable 1 00 00x xxxx xxxx 14 00 xxxx xxxx 13 erase erase byte or word 1 11 a10-a0 14 a9-a0 13 eral erase all memory 1 00 10x xxxx xxxx 14 10 xxxx xxxx 13 wral write all memory with same data 100 01x xxxx xxxx d7-d0 22 01 xxxx xxxx d15-d0 29
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 6/27 figure 5. read, write, ewen, ewds sequences note: for the meanings of an, xn, qn and dn, see table 4, table 5 and table 6. read the read data from memory (read) instruction outputs serial data on serial data output (q). when the instruction is received, the op-code and address are decoded, and the data from the mem- ory is transferred to an output shift register. a dum- my 0 bit is output first, followed by the 8-bit byte or the 16-bit word, with the most significant bit first. output data changes are triggered by the rising edge of serial clock (c). the m93cx6 automati- cally increments the internal address register and clocks out the next byte (or word) as long as the chip select input (s) is held high. in this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. erase/write enable and disable the erase/write enable (ewen) instruction en- ables the future execution of erase or write instruc- tions, and the erase/write disable (ewds) instruction disables it. when power is first applied, the m93cx6 initializes itself so that erase and write instructions are disabled. after an erase/write en- able (ewen) instruction has been executed, eras- ing and writing remains enabled until an erase/ write disable (ewds) instruction is executed, or until v cc falls below the power-on reset threshold voltage. to protect the memory contents from ac- cidental corruption, it is advisable to issue the erase/write disable (ewds) instruction after ev- ery write cycle. the read data from memory (read) instruction is not affected by the erase/ write enable (ewen) or erase/write disable (ewds) instructions. ai00878c 1 1 0 an a0 qn q0 data out d s q read s write addr op code 1 0an a0 data in d q op code dn d0 1 busy ready s erase write enable 1 0xnx0 d op code 1 01 s erase write disable 1 0xnx0 d op code 0 0 0 check status addr
7/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 figure 6. erase, eral sequences note: for the meanings of an and xn, please see table 4, table 5 and table 6. erase the erase byte or word (erase) instruction sets the bits of the addressed memory byte (or word) to 1. once the address has been correctly decoded, the falling edge of the chip select input (s) starts the self-timed erase cycle. the completion of the cycle can be detected by monitoring the ready/ busy line, as described on page 7. write for the write data to memory (write) instruction, 8 or 16 data bits follow the op-code and address bits. these form the byte or word that is to be writ- ten. as with the other bits, serial data input (d) is sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. the completion of the cycle can be detected by monitoring the ready/busy line, as described later in this document. once the write cycle has been started, it is inter- nally self-timed (the external clock signal on serial clock (c) may be stopped or left running after the start of a write cycle). the cycle is automatically preceded by an erase cycle, so it is unnecessary to execute an explicit erase instruction before a write data to memory (write) instruction. erase all the erase all memory (eral) instruction erases the whole memory (all memory bits are set to 1). the format of the instruction requires that a dum- my address be provided. the erase cycle is con- ducted in the same way as the erase instruction (erase). the completion of the cycle can be de- tected by monitoring the ready/busy line, as de- scribed on page 7. ai00879b s erase 1 1 d q addr op code 1 busy ready check status s erase all 1 0 d q op code 1 busy ready check status 0 0 an a0 xn x0 addr
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 8/27 figure 7. wral sequence note: for the meanings of xn and dn, please see table 4, table 5 and table 6. write all as with the erase all memory (eral) instruction, the format of the write all memory with same data (wral) instruction requires that a dummy ad- dress be provided. as with the write data to mem- ory (write) instruction, the format of the write all memory with same data (wral) instruction re- quires that an 8-bit data byte, or 16-bit data word, be provided. this value is written to all the ad- dresses of the memory device. the completion of the cycle can be detected by monitoring the ready/busy line, as described next. ready/busy status while the write or erase cycle is underway, for a write, erase, wral or eral instruction, the busy signal (q=0) is returned whenever chip se- lect input (s) is driven high. (please note, though, that there is an initial delay, of t slsh , before this status information becomes available). in this state, the m93cx6 ignores any data on the bus. when the write cycle is completed, and chip se- lect input (s) is driven high, the ready signal (q=1) indicates that the m93cx6 is ready to re- ceive the next instruction. serial data output (q) remains set to 1 until the chip select input (s) is brought low or until a new start bit is decoded. common i/o operation serial data output (q) and serial data input (d) can be connected together, through a current lim- iting resistor, to form a common, single-wire data bus. some precautions must be taken when oper- ating the memory in this way, mostly to prevent a short circuit current from flowing when the last ad- dress bit (a0) clashes with the first data bit on se- rial data output (q). please see the application note an394 for details. ai00880c s write all data in d q addr op code dn d0 busy ready check status 1 0 0 0 1 xn x0
9/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 figure 8. write sequence with one clock glitch clock pulse counter in a noisy environment, the number of pulses re- ceived on serial clock (c) may be greater than the number delivered by the master (the microcontrol- ler). this can lead to a misalignment of the instruc- tion of one or more bits (as shown in figure 8) and may lead to the writing of erroneous data at an er- roneous address. to combat this problem, the m93cx6 has an on- chip counter that counts the clock pulses from the start bit until the falling edge of the chip select in- put (s). if the number of clock pulses received is not the number expected, the write, erase, eral or wral instruction is aborted, and the contents of the memory are not modified. the number of clock cycles expected for each in- struction, and for each member of the m93cx6 family, are summarized in table 4 to table 6. for example, a write data to memory (write) in- struction on the m93c56 (or m93c66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of chip select input (s). that is: 1 start bit + 2 op-code bits + 9 address bits + 8 data bits ai01395 s an-1 c d write start d0 "1" "0" an glitch an-2 address and data are shifted by one bit
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 10/27 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 7. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 w , r2=500 w ) symbol parameter min. max. unit t stg storage temperature C65 150 c t lead lead temperature during soldering pdip: 10 seconds so: 20 seconds (max) 1 tssop: 20 seconds (max) 1 260 235 235 c v out output range (q = v oh or hi-z) C0.3 v cc +0.5 v v in input range C0.3 v cc +1 v v cc supply voltage C0.3 6.5 v v esd electrostatic discharge voltage (human body model) 2 C4000 4000 v
11/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 8. operating conditions (m93cx6) table 9. operating conditions (m93cx6-w) table 10. operating conditions (m93cx6-r) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (range 6) C40 85 c ambient operating temperature (range 3) C40 125 c symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature (range 6) C40 85 c ambient operating temperature (range 3) C40 125 c symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature (range 6) C40 85 c
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 12/27 table 11. ac measurement conditions (m93cx6) note: 1. output hi-z is defined as the point where data out is no longer driven. table 12. ac measurement conditions (m93cx6-w and m93cx6-r) note: 1. output hi-z is defined as the point where data out is no longer driven. figure 9. ac testing input output waveforms table 13. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 1 mhz. symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.4 v to 2.4 v v input timing reference voltages 1.0 v and 2.0 v v output timing reference voltages 0.8 v and 2.0 v v symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages 0.3v cc to 0.7v cc v symbol parameter test condition min max unit c out output capacitance v out = 0v 5pf c in input capacitance v in = 0v 5pf ai02553 2.4v 0.4v 2.0v 0.8v 2v 1v input output 0.8v cc 0.2v cc 0.7v cc 0.3v cc m93cxx-w & m93cxx-r m93cxx
13/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 table 14. dc characteristics (m93cx6, temperature range 6) note: 1. current product: identified by process identification letter f or m. 2. new product: identified by process identification letter w. table 15. dc characteristics (m93cx6, temperature range 3) note: 1. current product: identified by process identification letter f or m. 2. new product: identified by process identification letter w. symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current v cc = 5v, s = v ih , f = 1 mhz, current product 1 1.5 ma v cc = 5v, s = v ih , f = 2 mhz, new product 2 2 ma i cc1 supply current (stand-by) v cc = 5v, s = v ss , c = v ss , org = v ss or v cc , current product 1 50 a v cc = 5v, s = v ss , c = v ss , org = v ss or v cc , new product 2 15 a v il input low voltage v cc = 5v 10% C0.3 0.8 v v ih input high voltage v cc = 5v 10% 2 v cc + 1 v v ol output low voltage v cc = 5v, i ol = 2.1ma 0.4 v v oh output high voltage v cc = 5v, i oh = C400a 2.4 v symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current v cc = 5v, s = v ih , f = 1 mhz, current product 1 1.5 ma v cc = 5v, s = v ih , f = 2 mhz, new product 2 2 ma i cc1 supply current (stand-by) v cc = 5v, s = v ss , c = v ss , org = v ss or v cc , current product 1 50 a v cc = 5v, s = v ss , c = v ss , org = v ss or v cc , new product 2 15 a v il input low voltage v cc = 5v 10% C0.3 0.8 v v ih input high voltage v cc = 5v 10% 2 v cc + 1 v v ol output low voltage v cc = 5v, i ol = 2.1ma 0.4 v v oh output high voltage v cc = 5v, i oh = C400a 2.4 v
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 14/27 table 16. dc characteristics (m93cx6-w, temperature range 6) note: 1. current product: identified by process identification letter f or m. 2. new product: identified by process identification letter w. symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5v, s = v ih , f = 1 mhz, current product 1 1.5 ma v cc = 2.5v, s = v ih , f = 1 mhz, current product 1 1 ma v cc = 5v, s = v ih , f = 2 mhz, new product 2 2 ma v cc = 2.5v, s = v ih , f = 2 mhz, new product 2 1 ma i cc1 supply current (stand-by) v cc = 2.5v, s = v ss , c = v ss , org = v ss or v cc , current product 1 10 a v cc = 2.5v, s = v ss , c = v ss , org = v ss or v cc , new product 2 5 a v il input low voltage (d, c, s) C0.3 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.4 v v cc = 2.5v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = C400a 2.4 v v cc = 2.5v, i oh = C100a v cc C0.2 v
15/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 table 17. dc characteristics (m93cx6-w, temperature range 3) note: 1. new product: identified by process identification letter w. table 18. dc characteristics (m93cx6-r) note: 1. this product is under development. for more infomation, please contact your nearest st sales office. symbol parameter test condition min. 1 max. 1 unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5v, s = v ih , f = 2 mhz 2 ma v cc = 2.5v, s = v ih , f = 2 mhz 1 ma i cc1 supply current (stand-by) v cc = 2.5v, s = v ss , c = v ss , org = v ss or v cc 5 a v il input low voltage (d, c, s) C0.3 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5v, i ol = 2.1ma 0.4 v v cc = 2.5v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 5v, i oh = C400a 2.4 v v cc = 2.5v, i oh = C100a v cc C0.2 v symbol parameter test condition min. 1 max. 1 unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5v, s = v ih , f = 2 mhz 2 ma v cc = 1.8v, s = v ih , f = 1 mhz 1 ma i cc1 supply current (stand-by) v cc = 1.8v, s = v ss , c = v ss , org = v ss or v cc 2 a v il input low voltage (d, c, s) C0.3 0.2 v cc v v ih input high voltage (d, c, s) 0.8 v cc v cc + 1 v v ol output low voltage (q) v cc = 1.8v, i ol = 100a 0.2 v v oh output high voltage (q) v cc = 1.8v, i oh = C100a v cc C0.2 v
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 16/27 table 19. ac characteristics (m93cx6, temperature range 6 or 3) note: 1. t chcl + t clch 3 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. current product: identified by process identification letter f or m. 4. new product: identified by process identification letter w. test conditions specified in table 11 and table 8 symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sk clock frequency d.c. 1 d.c. 2 mhz t slch chip select low to clock high 250 50 ns t shch t css chip select set-up time m93c46, m93c56, m93c66 50 50 ns chip select set-up time m93c76, m93c86 100 50 ns t slsh 2 t cs chip select low to chip select high 250 200 ns t chcl 1 t skh clock high time 250 200 ns t clch 1 t skl clock low time 250 200 ns t dvch t dis data in set-up time 100 50 ns t chdx t dih data in hold time 100 50 ns t clsh t sks clock set-up time (relative to s) 100 50 ns t clsl t csh chip select hold time 0 0 ns t shqv t sv chip select to ready/busy status 400 200 ns t slqz t df chip select low to output hi-z 200 100 ns t chql t pd0 delay to output low 400 200 ns t chqv t pd1 delay to output valid 400 200 ns t w t wp erase/write cycle time 10 5 ms
17/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 table 20. ac characteristics (m93cx6-w, temperature range 6) note: 1. t chcl + t clch 3 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. current product: identified by process identification letter f or m. 4. new product: identified by process identification letter w. test conditions specified in table 12 and table 9 symbol alt. parameter min. 3 max. 3 min. 4 max. 4 unit f c f sk clock frequency d.c. 1 d.c. 2 mhz t slch chip select low to clock high 250 50 ns t shch t css chip select set-up time 100 50 ns t slsh 2 t cs chip select low to chip select high 1000 200 ns t chcl 1 t skh clock high time 350 200 ns t clch 1 t skl clock low time 250 200 ns t dvch t dis data in set-up time 100 50 ns t chdx t dih data in hold time 100 50 ns t clsh t sks clock set-up time (relative to s) 100 50 ns t clsl t csh chip select hold time 0 0 ns t shqv t sv chip select to ready/busy status 400 200 ns t slqz t df chip select low to output hi-z 200 100 ns t chql t pd0 delay to output low 400 200 ns t chqv t pd1 delay to output valid 400 200 ns t w t wp erase/write cycle time 10 5 ms
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 18/27 table 21. ac characteristics (m93cx6-w, temperature range 3) note: 1. t chcl + t clch 3 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. new product: identified by process identification letter w. test conditions specified in table 12 and table 9 symbol alt. parameter min. 3 max. 3 unit f c f sk clock frequency d.c. 2 mhz t slch chip select low to clock high 50 ns t shch t css chip select set-up time 50 ns t slsh 2 t cs chip select low to chip select high 200 ns t chcl 1 t skh clock high time 200 ns t clch 1 t skl clock low time 200 ns t dvch t dis data in set-up time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock set-up time (relative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase/write cycle time 5 ms
19/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 table 22. ac characteristics (m93cx6-r) note: 1. t chcl + t clch 3 1 / f c . 2. chip select input (s) must be brought low for a minimum of tslsh between consecutive instruction cycles. 3. this product is under development. for more infomation, please contact your nearest st sales office. test conditions specified in table 12 and table 10 symbol alt. parameter min. 3 max. 3 unit f c f sk clock frequency d.c. 1 mhz t slch chip select low to clock high 250 ns t shch t css chip select set-up time 50 ns t slsh 2 t cs chip select low to chip select high 250 ns t chcl 1 t skh clock high time 250 ns t clch 1 t skl clock low time 250 ns t dvch t dis data in set-up time 100 ns t chdx t dih data in hold time 100 ns t clsh t sks clock set-up time (relative to s) 100 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 400 ns t slqz t df chip select low to output hi-z 200 ns t chql t pd0 delay to output low 400 ns t chqv t pd1 delay to output valid 400 ns t w t wp erase/write cycle time 10 ms
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 20/27 figure 10. synchronous timing (start and op-code input) figure 11. synchronous timing (read or write) figure 12. synchronous timing (read or write) ai01428 c op code op code start s d op code input start tdvch tshch tclsh tchcl tclch tchdx ai00820c c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15/q7 q0 ai01429 c d q address/data input hi-z tdvch tslch a0/d0 s write cycle tslsh tchdx an tclsl tslqz busy tshqv tw ready
21/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 package mechanical pdip8 C 8 pin plastic dip, 0.25mm lead frame, package outline notes: 1. drawing is not to scale. pdip8 C 8 pin plastic dip, 0.25mm lead frame, package mechanical data pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 C C 0.100 C C ea 7.62 C C 0.300 C C eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 22/27 so8 narrow C 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. so8 narrow C 8 lead plastic small outline, 150 mils body width, package mechanical data so-a e n cp b e a d c l a1 a 1 h h x 45? symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e 1.27 C C 0.050 C C h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 a 0 8 0 8 n8 8 cp 0.10 0.004
23/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 tssop8 3x3mm2 C 8 lead thin shrink small outline, 3x3mm2 body size, package outline notes: 1. drawing is not to scale. tssop8 3x3mm2 C 8 lead thin shrink small outline, 3x3mm2 body size, package mechanical data tssop8bm 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.100 0.0433 a1 0.050 0.150 0.0020 0.0059 a2 0.850 0.750 0.950 0.0335 0.0295 0.0374 b 0.250 0.400 0.0098 0.0157 c 0.130 0.230 0.0051 0.0091 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 4.900 4.650 5.150 0.1929 0.1831 0.2028 e1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C cp 0.100 0.0039 l 0.550 0.400 0.700 0.0217 0.0157 0.0276 l1 0.950 0.0374 a 0 6 0 6
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 24/27 tssop8 C 8 lead thin shrink small outline, package outline notes: 1. drawing is not to scale. tssop8 C 8 lead thin shrink small outline, package mechanical data tssop8am 1 8 cp c l e e1 d a2 a a e b 4 5 a1 l1 symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 C C 0.0256 C C e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 a 0 8 0 8
25/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 part numbering table 23. ordering information scheme note: 1. produced with high reliability certified flow (hrcf). 2. m93c06 is not for new design. 3. available only on new products: identified by the process identification letter w. 4. turned die option is not available for all devices. please contact your nearest stmicroelectronics sales office. devices are shipped from the factory with the memory content set at all 1s (ffffh for x16, ffh for x8). for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. table 24. how to identify current and new products by the process identification letter note: 1. this example comes from the s08 package. other packages have similar information. for further information, please ask yo ur st sales office for process change notice pcn mpg/ee/0059 (pcee0059). example: m93c86 Ctwmn6t device type m93 = microwire serial access eeprom device function 86 = 16 kbit (2048 x 8) 76 = 8 kbit (1024 x 8) 66 = 4 kbit (512 x 8) 56 = 2 kbit (256 x 8) 46 = 1 kbit (128 x 8) 06 2 = 256 bit (32 x 8) turned die blank = normal (unturned) die t 4 = 90 turned die operating voltage blank = v cc = 4.5 to 5.5v w = v cc = 2.5 to 5.5v r = v cc = 1.8 to 5.5v package bn = pdip8 mn = so8 (150 mil width) dw = tssop8 (169 mil width) ds 3 = tssop8 (3x3mm body size) temperature range 6 = C40 to 85 c 3 1 = C40 to 125 c option t = tape & reel packing markings on current products 1 markings on new products 1 m93c46w6 ayww f (or ayww m ) m93c46w6 ayww w
m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 26/27 revision history table 25. document revision history date rev. description of revision 04-feb-2003 2.0 document reformatted, and reworded, using the new template. temperature range 1 removed. tssop8 (3x3mm) package added. new products, identified by the process letter w, added, with fc(max) increased to 1mhz for -r voltage range, and to 2mhz for all other ranges (and corresponding parameters adjusted) 26-mar-2003 2.1 value of standby current (max) corrected in dc characteristics tables for -w and -r ranges v out and v in separated from v io in the absolute maximum ratings table 04-apr-2003 2.2 values corrected in ac characteristics tables for -w range (tslsh, tdvch, tclsl) for devices with process identification letter w 23-may-2003 2.3 standby current corrected for -r range 27-may-2003 2.4 turned die option re-instated in ordering information scheme
27/27 m93c86, m93c76, m93c66, m93c56, m93c46, m93c06 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

▲Up To Search▲

Price & Availability of M93C06-TRMN6T

	To Download M93C06-TRMN6T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .